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CY28442-2
Clock Generator for Intel Alviso Chipset
Features
* Compliant to Intel CK410M * Supports Intel Pentium-M CPU * Selectable CPU frequencies * Differential CPU clock pairs * 100-MHz differential SRC clocks * 96-MHz differential dot clock * 48-MHz USB clocks * SRC clocks independently stoppable through CLKREQ#[A:B] * 96-/100-MHz Spreadable differential clock. * 33-MHz PCI clock * Low-voltage frequency select input * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin TSSOP package
CPU x2 / x3 SRC x5/6 PCI x6 REF x2 DOT96 x2 USB_48 x1
Block Diagram
VDD_REF REF IREF VDD_CPU CPUT CPUC VDD_CPU CPUT_ITP/SRCT7 CPUC_ITP/SRCC7 VDD_SRC SRCT[1:5] CPUC[1:5] VDD_PCI PCI VDD_PCI PCIF PLL2 96MSS VDD_48MHz 96_100_SSCT 96_100_SSCC VDD_48MHz DOT96T DOT96C VDD_48 VTTPWR_GD#/PD USB
Pin Configuration
XIN XOUT PCI_STP# CPU_STP# CLKREQ[A:B]# FS_[C:A]
14.318MHz Crystal
PLL Reference
PLL1 CPU
Divider
Divider
PLL3 FIXED
Divider
VDD_REF VSS_REF PCI3 PCI4 PCI5 VSS_PCI VDD_PCI ITP_EN/PCIF0 **96_100_SEL/PCIF1 VTTPWRGD#/PD VDD_48 FS_A/48M_0 VSS_48 DOT96T DOT96C FS_B/TESTMODE 96_100_SSCT 96_100_SSCC SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRCT4_SATA SRCC4_SATA VDD_SRC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCI2/SEL_CLKREQ** PCI_STP# CPU_STP# FS_C(TEST_SEL)/REF0 REF1 VSSA2 XIN XOUT VDDA2 SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPU2T_ITP/SRCT7 CPU2C_ITP/SRCC7 VDD_SRC_ITP CLKREQA#/SRCT6 CLKREQB#/SRCC6 SRCT5 SRCC5 VSS_SRC
SDATA SCLK
I2C Logic
56 pin TSSOP/SSOP
CY28442-2
Cypress Semiconductor Corporation Document #: 38-07691 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised August 3, 2005
CY28442-2
Pin Definitions
Pin No. 1 2 33,32 Name VDD_REF VSS_REF Type PWR GND 3.3V power supply for output Ground for outputs. Description
CLKREQA#/SRCT6, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz CLKREQB#,SRCC6 Serial Reference Clock. Selectable through CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte 8. VDD_PCI VSS_PCI PCI ITP_EN/PCIF0 PWR GND 3.3V power supply for outputs. Ground for outputs.
7 6 3,4,5 8
O, SE 33-MHz clock I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33-MHz clock output. (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 I/O, 33-MHz clock/3.3V-tolerant input for 96_100M frequency selection PD,SE (sampled on the VTT_PWRGD# assertion). 1 = 100 MHz, 0 = 96 MHz I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). 3.3V power supply for outputs. 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. Ground for outputs. 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
9
PCIF1/96_100_SEL
10
VTT_PWRGD#/PD
11 12 13 14,15 16
VDD_48 FS_A/48_M0 VSS_48 DOT96T, DOT96C FS_B/TEST_MODE
PWR I/O GND I
O, DIF Fixed 96-MHz clock output.
17,18
96_100_SSC
O,DIF Differential 96-/100-MHz SS clock for flat-panel display O, DIF 100-MHz Differential serial reference clocks. PWR PWR 3.3V power supply for outputs. 3.3V power supply for outputs.
19,20,22,23, SRCT/C 24,25,30,31 21,28 34 26,27 29 36,35 VDD_SRC VDD_SRC_ITP SRC4_SATAT, SRC4_SATAC VSS_SRC
O, DIF Differential serial reference clock. Recommended output for SATA. GND Ground for outputs.
CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output. CPUC2_ITP/SRCC7 ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 VDDA VSSA IREF VDD_CPU CPUT/C VSS_CPU SCLK SDATA PWR GND I PWR GND I I/O 3.3V power supply for PLL. Ground for PLL. A precision resistor is attached to this pin, which is connected to the internal current reference. 3.3V power supply for outputs. Ground for outputs. SMBus-compatible SCLOCK. SMBus-compatible SDATA.
37 38 39 42 44,43,41,40 45 46 47
O, DIF Differential CPU clock outputs.
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CY28442-2
Pin Definitions (continued)
Pin No. 48 49 50 51 52 53 VDDA2 XOUT XIN VSSA2 REF1 FS_C_TEST_SEL/ REF0 Name Type PWR I GND O I/O 3.3V power supply for PLL2 14.318-MHz crystal input. Ground for PLL2. Fixed 14.318 MHz clock output. 3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. 3.3V LVTTL input for CPU_STP# active LOW. 3.3V LVTTL input for PCI_STP# active LOW. O, SE 14.318-MHz crystal output. Description
54 55 56
CPU_STP# PCI_STP#
I, PU I, PU
PCI2/SEL_CLKREQ I/O, PD 3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output. (sampled on the VTT_PWRGD# assertion). 1= pins 32,33 function as clk request pins, 0= pins 32,33 function as SRC outputs.
Table 1. Frequency Select Table FS_A, FS_B, and FS_C FS_C 1 0 0 0 FS_B 0 0 1 1 FS_A 1 1 1 0 CPU 100 MHz 133 MHz 166 MHz 200 MHz SRC 100 MHz 100 MHz 100 MHz 100 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz 33 MHz REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz DOT96 96 MHz 96 MHz 96 MHz 96 MHz USB 48 MHz 48 MHz 48 MHz 48 MHz
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C input values. For all logic levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, and FS_C transitions will be ignored, except in test mode.
initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 2. Command Code Definition Bit 7 (6:0)
Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
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CY28442-2
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
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Control Registers
Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 SRC[T/C]6 SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 RESERVED Description CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable RESERVED
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Name PCIF0 DOT_96T/C USB_48 REF0 REF1 CPU[T/C]1 CPU[T/C]0 CPU Description PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled REF1 Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI5 PCI4 PCI3 PCI2 Reserved Reserved Reserved PCIF1 Description PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled
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CY28442-2
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC7 SRC6 SRC5 SRC4 SRC3 SRC2 SRC1 RESERVED Description Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name 96_100_SSC DOT96T/C RESERVED PCIF1 PCIF0 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Description 96_100_SSC Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state RESERVED Allow control of PCIF1 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C] Description SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP# asserted CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted
6
0
CPU[T/C]2
5
0
CPU[T/C]1
4
0
CPU[T/C]0
3 2 1
0 0 0
SRC[T/C][7:1] CPU[T/C]2 CPU[T/C]1
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CY28442-2
Byte 5: Control Register 5 (continued) Bit 0 @Pup 0 Name CPU[T/C]0 Description CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 0 1 1 REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock TEST_MODE Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, RESERVED RESERVED REF REF Output Drive Strength 0 = Low, 1 = High PCI, PCIF and SRC clock SW PCI_STP Function outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will to free running be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. FS_C FS_C Reflects the value of the FS_C pin sampled on power-up 0 = FS_C was low during VTT_PWRGD# assertion FS_B FS_B Reflects the value of the FS_B pin sampled on power-up 0 = FS_B was low during VTT_PWRGD# assertion FS_A FS_A Reflects the value of the FS_A pin sampled on power-up 0 = FS_A was low during VTT_PWRGD# assertion Name TEST_SEL Description
2 1 0
HW HW HW
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
Byte 8: Control Register 8 Bit 7 @Pup 0 Name CLKREQ#B Description SRC[T/C]7CLKREQ#B control 1 = SRC[T/C]7 stoppable by CLKREQ#B pin 0 = SRC[T/C]7 not controlled by CLKREQ#B pin SRC[T/C]5 CLKREQ#B control 1 = SRC[T/C]5 stoppable by CLKREQ#B pin 0 = SRC[T/C]5 not controlled by CLKREQ#B pin SRC[T/C]3 CLKREQ#B control 1 = SRC[T/C]3 stoppable by CLKREQ#B pin 0 = SRC[T/C]3 not controlled by CLKREQ#B pin SRC[T/C]1 CLKREQ#B control 1 = SRC[T/C]1 stoppable by CLKREQ#B pin 0 = SRC[T/C]1 not controlled by CLKREQ#B pin RESERVED SRC[T/C]4 CLKREQ#A control 1 = SRC[T/C]4 stoppable by CLKREQ#A pin 0 = SRC[T/C]4 not controlled by CLKREQ#A pin Page 7 of 21
6
1
CLKREQ#B
5
0
CLKREQ#B
4
0
CLKREQ#B
3 2
0 1
RESERVED CLKREQ#A
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CY28442-2
Byte 8: Control Register 8 (continued) Bit 1 @Pup 0 Name CLKREQ#A Description SRC[T/C]2 CLKREQ#A control 1 = SRC[T/C]2 stoppable by CLKREQ#A pin 0 = SRC[T/C]2 not controlled by CLKREQ#A pin RESERVED
0
0
RESERVED
Byte 9: Control Register 9 Bit 7 6 5 4 @Pup 0 0 0 0 Name S3 S2 S1 S0 Description 96_100_SSC Spread Spectrum Selection table: S[3:0] SS% `0000' = -0.8%(Default value) `0001' = -1.0% `0010' = -1.25% `0011' = -1.5% `0100' = -1.75% `0101' = -2.0% `0110' = -2.5% `0111' = -0.5% `1000' = 0.25% `1001' = 0.4% `1010' = 0.5% `1011' = 0.6% `1100' = 0.8% `1101' = 1.0% `1110' = 1.25% `1111' = 1.5% Software select 96_100_SSC output frequency, 0 = 96 MHz, 1 = 100 MHz. 96_100_SSC Enable, 0 = Disable, 1 = Enable. 96_100_SSC Spread spectrum enable. 0 = Disable, 1 = Enable. Select output frequency of 96_100_SSC via software or hardware 0 = Hardware, 1 = Software.
3 2 1 0
1 1 1 0
96_100 SEL 96_100 Enable 96_100 SS Enable 96_100 SW HW
Byte 10: Control Register 10 Bit 7 6 @Pup 0 0 Name RESERVED CLKREQ#B Description RESERVED SRC[T/C]4 CLKREQ#B control 1 = SRC[T/C]4 stoppable by CLKREQ#B pin 0 = SRC[T/C]4not controlled by CLKREQ#B pin SRC[T/C]2 CLKREQ#B control 1 = SRC[T/C]2 stoppable by CLKREQ#B pin 0 = SRC[T/C]2 not controlled by CLKREQ#B pin RESERVED SRC[T/C]7CLKREQ#A control 1 = SRC[T/C]7 stoppable by CLKREQ#A pin 0 = SRC[T/C]7 not controlled by CLKREQ#A pin SRC[T/C]5 CLKREQ#A control 1 = SRC[T/C]5 stoppable by CLKREQ#A pin 0 = SRC[T/C]5 not controlled by CLKREQ#A pin SRC[T/C]3 CLKREQ#A control 1 = SRC[T/C]3 stoppable by CLKREQ#A pin 0 = SRC[T/C]3 not controlled by CLKREQ#A pin SRC[T/C]1 CLKREQ#A control 1 = SRC[T/C]1 stoppable by CLKREQ#A pin 0 = SRC[T/C]1 not controlled by CLKREQ#A pin
5
0
CLKREQ#B
4 3
0 0
RESERVED CLKREQ#A
2
0
CLKREQ#A
1
0
CLKREQ#A
0
0
CLKREQ#A
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CY28442-2
Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW
.
Shunt Cap (max.) 5 pF
Motional (max.) 0.016 pF
Tolerance (max.) 35 ppm
Stability (max.) 30 ppm
Aging (max.) 5 ppm
The CY28442-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28442-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Clock Chip
Ci1
Ci2 Pin 3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
X1 X2
Cs1
Cs2 Trace 2.8pF
XTAL Ce1 Ce2
Trim 33pF
Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides.
Figure 1. Crystal Capacitive Clarification
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CLK_REQ[0:1]# Description The CLKREQ#[A:B] signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ#[A:B] are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it's state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous).
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CLKREQ#X
SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable)
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2 and 6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater than 200 mV. CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ#[A:B] pins is that all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ#[A:B] are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF
internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock output are held with "Diff clock" pin driven HIGH at 2 x Iref, and "Diff clock#" tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are tri-state. Note the example below shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#.
Figure 4. Power-down Assertion Timing Waveform
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PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two-six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to 6 x (Iref), and the CPUC signal will be tri-stated.
Tstable <1.8nS
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300S, >200mV
Figure 5. Power-down Deassertion Timing Waveform
CPU_STP# CPUT CPUC
Figure 6. CPU_STP# Assertion Waveform
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CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP# CPUT CPUC CPUT Internal CPUC Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 7. CPU_STP# Deassertion Waveform
1.8mS CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
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PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free-running. PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level.
PCI_STP# PCI_F
Tsu
PCI SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
Tsu Tdrive_SRC
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM
VDD Clock Gen Clock State State 0 Off Off
0.2-0.3mS Delay State 1
W ait for VTT_PW RGD#
Sample Sels State 2 State 3 On
Device is not affected, VTT_PW RGD# is ignored
Clock Outputs Clock VCO
On
Figure 12. VTT_PWRGD# Timing Diagram
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S1 S2 VTT_PWRGD# = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 13. Clock Generator Power-up/Run State Diagram
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CY28442-2
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-STD-883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 85 150 20 60 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter All VDDs VILI2C VIHI2C VIL_FS VIH_FS VILFS_C VIMFS_C VIHFS_C VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPD3.3V ITRI Description 3.3V Operating Voltage Input Low Voltage Input High Voltage FS_[A,B] Input Low Voltage FS_[A,B] Input High Voltage FS_C Input Low Voltage FS_C Input Middle Voltage FS_C Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage Input Low Leakage Current Input High Leakage Current 3.3V Output Low Voltage 3.3V Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Power-down Supply Current Tri-state Current At max. load and freq. per Figure 15 PD asserted, Outputs Driven PD asserted, Outputs Tri-state Current in tri-state mode Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA 3.3 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS - 0.3 0.7 VSS - 0.3 0.7 1.8 VSS - 0.3 2.0 -5 - - 2.4 -10 3 3 - 0.7VDD 0 - - - - Max. 3.465 1.0 - 0.35 VDD + 0.5 0.35 1.8 VDD + 0.5 0.8 VDD + 0.3 5 5 0.4 - 10 5 5 7 VDD 0.3VDD 400 70 2 100 Unit V V V V V V V V V V A A V V A pF pF nH V V mA mA mA mA
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AC Electrical Specifications
Parameter Crystal TDC TPERIOD TR / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIOD TPERIOD TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1-s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Min. 47.5 Max. 52.5 Unit %
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 166-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period
69.841 - - - 45 9.997001 7.497751 5.998201 4.998500 9.997001 7.497751 5.998201 4.998500 9.912001 7.412751 5.913201 4.913500 9.912001 7.412751 5.913201 4.913500 - - - 175 - - -
71.0 10.0 500 300 55 10.00300 7.502251 6.001801 5.001500 10.05327 7.539950 6.031960 5.026634 10.08800 7.587251 6.086801 5.086500 10.13827 7.624950 6.116960 5.111634 85 125 150 700 20 125 125 850 - 550
ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps mV mV mV
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 100-MHz CPUT and CPUC Absolute period 133-MHz CPUT and CPUC Absolute period 166-MHz CPUT and CPUC Absolute period 200-MHz CPUT and CPUC Absolute period Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC TCCJ TCCJ2 TSKEW2 TR / TF TRFM TR TF VHIGH VLOW VOX CPUT/C Cycle to Cycle Jitter CPU2_ITP Cycle to Cycle Jitter CPU2_ITP to CPU0 Clock Skew CPUT and CPUC Rise and Fall Time Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing
Math averages Figure 15 Math averages Figure 15
660 -150 250
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AC Electrical Specifications (continued)
Parameter VOVS VUDS VRB SRC TDC TPERIOD TPERIODSS TPERIODAbs Description Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period 100-MHz SRCT and SRCC Absolute Period See Figure 15. Measure SE Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Condition Min. - -0.3 - 45 9.997001 9.997001 9.872001 9.872001 - - - 175 - - - Math averages Figure 15 Math averages Figure 15 660 -150 250 - -0.3 See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX - 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 1.0 - - 45 10.41354 10.16354 - - Max. VHIGH + 0.3 - 0.2 55 10.00300 10.05327 10.12800 10.17827 100 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 30.00900 30.15980 30.50900 30.65980 - - 4.0 500 500 55 10.41979 10.66979 250 100 Unit V V V % ns ns ns ns ps ps ppm ps % ps ps mV mV mV V V V % ns ns ns ns ns ns V/ns ps ps % ns ns ps ppm
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC TSKEW TCCJ LACC TR / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB PCI/PCIF TDC TPERIOD TPERIODSS TPERIODAbs THIGH TLOW TR / TF TSKEW TCCJ DOT TDC TPERIOD TPERIODAbs TCCJ LACC Any SRCT/C to SRCT/C Clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Time Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Disabled PCIF/PCI Period PCIF and PCI high time PCIF and PCI low time PCIF/PCI rising and falling Edge Rate Any PCI clock to Any PCI clock Skew PCIF and PCI Cycle to Cycle Jitter DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
DOT96T and DOT96C Absolute Period Measured at crossing point VOX
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CY28442-2
AC Electrical Specifications (continued)
Parameter TR / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB USB TDC TPERIOD TPERIODAbs THIGH TLOW TR / TF TCCJ REF TDC TPERIOD TPERIODAbs TR / TF TCCJ Description DOT96T and DOT96C Rise and Fall Time Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Duty Cycle Period Absolute Period USB high time USB low time Rising and Falling Edge Rate Cycle to Cycle Jitter REF Duty Cycle REF Period REF Absolute Period REF Rising and Falling Edge Rate REF Cycle to Cycle Jitter See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Math averages Figure 15 Math averages Figure 15 Condition Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. 175 - - - 660 -150 250 - -0.3 - 45 20.83125 20.48125 8.094 7.694 1.0 - 45 69.8203 68.82033 1.0 - - 10.0 0 Max. 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 20.83542 21.18542 10.036 9.836 2.0 350 55 69.8622 70.86224 4.0 1000 1.8 - - Unit ps % ps ps mV mV mV V V V % ns ns ns ns V/ns ps % ns ns V/ns ps ms ns ns
ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
Test and Measurement Set-up
For PCI Single-ended Signals and Reference The following diagram shows the single-ended PCI outputs.
tDC 3.3V 2.4V 1.5V 0.4V 0V Tr Tf Output under Test Probe 30 pF Load Cap
Figure 14. Single-ended PCI Lumped Load Configuration
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CY28442-2
The following diagram shows the test load configuration for the differential CPU and SRC outputs.
CPUT SRCT D O T96T 96_100SSC T CPUC SRCC D O T96C 96_100SSC C IR E F 475
33 4 9 .9 33 4 9 .9
1 0 0 D if f e r e n t ia l
M e a s u re m e n t P o in t
2pF
M e a s u re m e n t P o in t
2pF
Figure 15. 0.7V Differential Clock Load Configuration
3 .3 V s ig n a l s
-
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Lead-free CY28442ZXC-2 CY28442ZXC-2T 56-pin TSSOP 56-pin TSSOP - Tape and Reel Commercial, 0 to 85C Commercial, 0 to 85C Package Type Product Flow
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CY28442-2
Package Diagrams
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.170[0.006] 0.279[0.011]
0.100[0.003] 0.200[0.008]
51-85060-*C
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28442-2
Document History Page
Document Title: CY28442-2 Clock Generator for Intel Alviso Chipset Document Number: 38-07691 REV. ** *A *B ECN NO. 237627 378059 390510 Issue Date See ECN See ECN See ECN Orig. of Change RGL RGL RGL New Data Sheet Minor Change: Corrected typo in the label of the diagram from PLL4 to PLL3 Removed Preliminary Description of Change
Document #: 38-07691 Rev. *B
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